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?1 e98y43-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP922032 cmos 16-bit single chip microcomputer description the CXP922032 is a cmos 16-bit microcomputer integrating on a single chip an a/d converter, serial interface, timer, remote control receive circuit, pwm output circuit, and as well as basic configurations like a 16-bit cpu, rom, ram, and i/o port. this lsi also provides the sleep/stop functions that enable lower power consumption. features an efficient instruction set as a controller ?direct addressing, numerous abbreviated forms, multiplication and division instructions instruction sets for c language and rtos ?highly quadratic instruction system, general-purpose register of eight 16-bit 16-bank configuration minimum instruction cycle 100ns/20mhz operation (3.0 to 5.5v) 167ns/12mhz operation (2.7 to 5.5v) incorporated rom capacity 128k bytes incorporated ram capacity 7680 bytes peripheral functions ?a/d converter 8-bit 8 analog input, successive approximation system (conversion time: 12.4s at 20mhz) ?serial interface asynchronous serial interface (simple uart) 128-byte buffer ram,3 channels ?timers 8-bit timer/counter, 2 channels (with timing output) 16-bit capture timer/counter (with timing output) 16-bit timer, 4 channels remote control receive circuit 8-bit pulse measurement counter, 8-stage fifo ?pwm output circuit 14-bit, 1 channel interruption 24 factors, 24 vectors, multi-interruption and priority selection possible standby mode sleep/stop package 100-pin plastic qfp piggy/evaluation chip cxp922000 one-time prom incorporated version cxp922p032 structure silicon gate cmos ic 100 pin qfp (plastic)
? 2 CXP922032 block diagram a / d c o n v e r t e r 8 5 7 a n 0 t o a n 7 p a 0 t o p a 7 v s s v d d a v r e f a v s s a v d d r s t x t a l e x t a l n m i i n t 0 t o i n t 4 p b 0 t o p b 7 p c 0 t o p c 7 p d 0 t o p d 7 p e 0 t o p e 7 p f 0 t o p f 5 p f 6 , p f 7 p g 0 t o p g 7 p h 0 t o p h 7 p i 0 t o p i 7 p j 0 t o p j 6 r x d t x d p w m r m c c s 0 s o 0 s i 0 s c k 0 s i 1 c s 1 s c k 1 s o 1 c s 2 s o 2 s i 2 s c k 2 t o 0 e c 0 e c 1 c i n t t o 1 s p c 9 5 0 c p u c o r e c l o c k g e n e r a t o r / s y s t e m c o n t r o l l e r p o r t a u a r t 1 4 - b i t p w m g e n e r a t o r r e m o c o n 4 c h 1 6 - b i t t i m e r f i f o s e r i a l i n t e r f a c e u n i t ( c h 0 ) b u f f e r r a m s e r i a l i n t e r f a c e u n i t ( c h 1 ) b u f f e r r a m s e r i a l i n t e r f a c e u n i t ( c h 2 ) b u f f e r r a m 8 - b i t t i m e r / c o u n t e r ( c h 0 ) 8 - b i t t i m e r ( c h 1 ) 1 6 - b i t c a p t u r e t i m e r / c o u n t e r ( c h 4 ) p r e s c a l e r / t i m e - b a s e t i m e r 2 r o m 1 2 8 k b y t e s 8 p o r t b 8 p o r t c 8 p o r t d i n t e r r u p t c o n t r o l l e r 8 p o r t e 8 p o r t f 6 2 p o r t g 8 p o r t h 8 p o r t i 8 p o r t j 7 r a m 7 6 8 0 b y t e s k s 0 t o k s 6 2 4
? 3 CXP922032 pin assignment (top view) 100-pin qfp package 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 0 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 9 9 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 p e 7 p f 0 / i n t 0 p f 1 / i n t 1 p f 2 / i n t 2 p f 3 / i n t 3 p f 4 / i n t 4 p f 5 / n m i p f 6 / t o 0 p f 7 / t o 1 / p w m r s t v s s x t a l e x t a l v d d a n 0 a n 1 a n 2 a n 3 p g 0 / a n 4 p g 1 / a n 5 p i 7 / r m c p i 6 / c i n t p i 5 / e c 1 p i 4 / e c 0 p i 3 p i 2 p i 1 / r x d p i 0 / t x d p h 7 / s c k 2 p h 6 / s o 2 p h 5 / s i 2 p h 4 / c s 2 p h 3 / s c k 1 p h 2 / s o 1 p h 1 / s i 1 p h 0 / c s 1 v s s s c k 0 s o 0 s i 0 c s 0 p g 7 p g 6 p g 5 p g 4 5 1 5 2 5 3 5 4 5 5 5 6 a v d d a v r e f a v s s p g 3 / a n 7 p g 2 / a n 6 p b 2 p b 3 p b 4 p b 5 p b 6 p b 7 p c 0 p c 1 p c 2 p c 3 p c 4 p c 5 p c 6 p c 7 v s s p d 0 p d 1 p d 2 p d 3 p d 4 p d 5 p d 6 p d 7 p e 0 2 5 2 6 2 7 2 8 2 9 p e 1 p e 2 p e 3 p e 4 p e 5 3 0 p e 6 p b 1 p b 0 p a 7 p a 6 p a 5 p a 4 p a 3 p a 2 p a 1 p a 0 v s s v d d n c p j 6 / k s 6 p j 5 / k s 5 p j 4 / k s 4 p j 3 / k s 3 p j 2 / k s 2 p j 1 / k s 1 p j 0 / k s 0 1 0 0 notes) 1. do not make any connections to nc (pin 88). 2. v ss (pins 15, 41, 64 and 90) must be connected to gnd. 3. v dd (pins 44 and 89) must be connected to v dd .
? 4 CXP922032 pin functions symbol i/o functions pa0 to pa7 i/o (port a) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 4-bit units. (8 pins) pb0 to pb7 i/o (port b) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 4-bit units. (8 pins) pc0 to pc7 i/o (port c) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 4-bit units. (8 pins) pd0 to pd7 i/o (port d) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 4-bit units. can drive 12ma sink current (v dd = 4.5 to 5.5v). (8 pins) pe0 to pe7 i/o (port e) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 4-bit units. can drive 12ma sink current (v dd = 4.5 to 5.5v). (8 pins) (port f) 8-bit port. lower 6 bits are for input; upper 2 bits are for output. (6 pins) pf0/int0 to pf4/int4 input / input external interrupt inputs. (4 pins) pf5/nmi input / input non-maskable interrupt input. pf6/to0 output / output 8-bit timer/counter output. pf7/to1/ pwm output / output / output 16-bit capture timer/ counter output. an0 to an3 input analog input for a/d converter. (4 pins) analog input for a/d converter. (4 pins) pg0/an4 to pg3/an7 i/o / input pg4 to pg7 i/o (port g) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 4-bit units. (8 pins) 14-bit pwm output. cs0 si0 so0 sck0 input input output i/o serial chip select (ch0) input. serial data (ch0) input. serial data (ch0) output. serial clock (ch0) i/o.
? 5 CXP922032 symbol i/o functions ph0/cs1 ph1/si1 ph2/so1 ph3/sck1 ph4/cs2 ph5/si2 ph6/so2 ph7/sck2 pi0/txd pi1/rxd pi2 to pi3 pi4/ec0 pi5/ec1 pi6/cint pi7/rmc pj0/ks0 to pj6/ks6 i/o / input i/o / input i/o / output i/o / i/o i/o / input i/o / input i/o / output i/o / i/o i/o / output i/o / input i/o i/o / input i/o / input i/o / input i/o / input i/o / input (port h) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 4-bit units. (8 pins) (port i) 8-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in 4-bit units. (8 pins) (port j) 7-bit i/o port. i/o can be specified in 1-bit units. pull-up resistor is present or not through program in lower 4-bit units and upper 3-bit units. (7 pins) serial chip select (ch1) input. serial data (ch1) input. serial data (ch1) output. serial clock (ch1) i/o. serial chip select (ch2) input. serial data (ch2) input. serial data (ch2) output. serial clock (ch2) i/o. uart transmission data output. uart reception data input. external event input for 8-bit timer/counter. external event input for 16-bit capture timer/ counter. external capture input for 16-bit capture timer/ counter. remote control receive circuit input. standby release input function can be specified in 1-bit units. (7 pins) extal xtal rst av dd av ref av ss v dd v ss nc input input input connects a crystal for system clock oscillation. (when the clock is supplied externally, input it to extal and input an opposite phase clock to xtal.) system reset. active at "l" level. positive power supply for a/d converter. reference voltage input for a/d converter. gnd for a/d converter. positive power supply. (connect both v dd pins to positive power supply.) gnd (connect all four v ss pins to gnd.) nc. (do not make any cunnection to nc.)
? 6 CXP922032 i/o circuit format for pins pin circuit format after a reset pa0 to pa7 hi-z p u l 0 r e g i s t e r " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s i n p u t p r o t e c t i o n c i r c u i t i p * * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) r d p a r e g i s t e r u n d e f i n e d a f t e r a r e s e t p a d r e g i s t e r " 0 " a f t e r a r e s e t pb0 to pb7 hi-z p u l 0 r e g i s t e r " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s i p * * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) r d p b r e g i s t e r u n d e f i n e d a f t e r a r e s e t p b d r e g i s t e r " 0 " a f t e r a r e s e t pc0 to pc7 hi-z p u l 0 r e g i s t e r " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s i p * * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) r d p c r e g i s t e r u n d e f i n e d a f t e r a r e s e t p c d r e g i s t e r " 0 " a f t e r a r e s e t
? 7 CXP922032 pin circuit format after a reset pd0 to pd7 hi-z pf0/int0 to pf4/int4 pf5/nmi hi-z p u l 0 r e g i s t e r " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s i p * 1 p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) * 2 l a r g e c u r r e n t d r i v e 1 2 m a ( v d d = 4 . 5 t o 5 . 5 v ) 4 . 5 m a ( v d d = 3 . 0 t o 3 . 6 v ) r d * 1 * 2 p d r e g i s t e r u n d e f i n e d a f t e r a r e s e t p d d r e g i s t e r " 0 " a f t e r a r e s e t pe0 to pe7 hi-z p u l 1 r e g i s t e r " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s i p * 1 p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) * 2 l a r g e c u r r e n t d r i v e 1 2 m a ( v d d = 4 . 5 t o 5 . 5 v ) 4 . 5 m a ( v d d = 3 . 0 t o 3 . 6 v ) r d * 1 * 2 p e r e g i s t e r u n d e f i n e d a f t e r a r e s e t p e d r e g i s t e r " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s c m o s s c h m i t t i n p u t r d i n t 0 , i n t 1 , i n t 2 , i n t 3 , i n t 4 , n m i i p
? 8 CXP922032 pin circuit format after a reset pf6/to0 "h" level pf7/to1/ pwm "h" level ("h" level at on resistance of pull-up transistor during a reset.) t o 0 r d i n t e r n a l d a t a b u s p f s l r e g i s t e r " 0 " a f t e r a r e s e t p f r e g i s t e r " 1 " a f t e r a r e s e t p f s l r e g i s t e r ( b i t 7 ) p f s l r e g i s t e r ( b i t 6 ) t o 1 o u t p u t e n a b l e t o 1 p w m * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 5 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 2 0 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) r d i n t e r n a l d a t a b u s i n t e r n a l r e s e t s i g n a l * 0 1 m p x 1 x 0 0 p f r e g i s t e r " 1 " a f t e r a r e s e t " 0 0 " a f t e r a r e s e t hi-z an0 to an3 i p a / d c o n v e r t e r i n p u t m u l t i p l e x e r
? 9 CXP922032 pin circuit format after a reset pg0/an4 to pg3/an7 hi-z * * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) i n t e r n a l d a t a b u s i p r d a / d c o n v e r t e r i n p u t m u l t i p l e x e r p u l 1 r e g i s t e r " 0 " a f t e r a r e s e t p g r e g i s t e r u n d e f i n e d a f t e r a r e s e t p g s l r e g i s t e r " 0 " a f t e r a r e s e t p g d r e g i s t e r " 0 " a f t e r a r e s e t pg4 to pg7 hi-z p u l 1 r e g i s t e r " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s i p * * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) r d p g r e g i s t e r u n d e f i n e d a f t e r a r e s e t p g d r e g i s t e r " 0 " a f t e r a r e s e t
? 10 CXP922032 ph0/cs1 ph1/si1 ph4/cs2 ph5/si2 hi-z * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) i n t e r n a l d a t a b u s i p r d c m o s s c h m i t t i n p u t * c s 1 , s i 1 , c s 2 , s i 2 p u l 1 r e g i s t e r " 0 " a f t e r a r e s e t p h r e g i s t e r u n d e f i n e d a f t e r a r e s e t p h d r e g i s t e r " 0 " a f t e r a r e s e t sck0 s c k 0 s c k 0 o u t p u t e n a b l e s c k 0 i p c m o s s c h m i t t i n p u t "h" level (hi-z during a reset) pin circuit format after a reset cs0 si0 hi-z hi-z so0 c m o s s c h m i t t i n p u t i p c s 0 s i 0 s o 0 s o 0 o u t p u t e n a b l e
? 11 CXP922032 pi0/txd hi-z * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) t x d o u t p u t e n a b l e i n t e r n a l d a t a b u s i p * r d t x d p u l 2 r e g i s t e r " 0 " a f t e r a r e s e t p i r e g i s t e r u n d e f i n e d a f t e r a r e s e t p i d r e g i s t e r " 0 " a f t e r a r e s e t pin circuit format after a reset ph2/so1 ph6/so2 hi-z * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) s o 1 , s o 2 o u t p u t e n a b l e i n t e r n a l d a t a b u s i p r d s o 1 , s o 2 * p u l 1 r e g i s t e r " 0 " a f t e r a r e s e t p h s l r e g i s t e r " 0 " a f t e r a r e s e t p h d r e g i s t e r " 0 " a f t e r a r e s e t p h r e g i s t e r u n d e f i n e d a f t e r a r e s e t ph3/sck1 ph7/sck2 hi-z s c k 1 , s c k 2 c m o s s c h m i t t i n p u t * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) s c k 1 , s c k 2 o u t p u t e n a b l e i n t e r n a l d a t a b u s i p r d s c k 1 , s c k 2 * p u l 1 r e g i s t e r " 0 " a f t e r a r e s e t p h s l r e g i s t e r " 0 " a f t e r a r e s e t p h d r e g i s t e r " 0 " a f t e r a r e s e t p h r e g i s t e r u n d e f i n e d a f t e r a r e s e t
? 12 CXP922032 pin circuit format after a reset pi1/rxd pi4/ec0 pi5/ec1 pi6/cint pi7/rmc hi-z * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) i n t e r n a l d a t a b u s i p r d c m o s s c h m i t t i n p u t * p u l 2 r e g i s t e r " 0 " a f t e r a r e s e t p i r e g i s t e r u n d e f i n e d a f t e r a r e s e t p i d r e g i s t e r " 0 " a f t e r a r e s e t r x d , e c 0 , e c 1 , c i n t , r m c pi2 to pi3 hi-z p u l 2 r e g i s t e r " 0 " a f t e r a r e s e t i n t e r n a l d a t a b u s i p * * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) r d p i r e g i s t e r u n d e f i n e d a f t e r a r e s e t p i d r e g i s t e r " 0 " a f t e r a r e s e t pj0/ks0 to pj6/ks6 hi-z * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 1 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 1 5 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) i n t e r n a l d a t a b u s s t a n d b y r e l e a s e i p * r d p u l 2 r e g i s t e r " 0 " a f t e r a r e s e t p j r e g i s t e r u n d e f i n e d a f t e r a r e s e t p j d r e g i s t e r " 0 " a f t e r a r e s e t
? 13 CXP922032 extal xtal oscillation "l" level (during a reset) rst d i a g r a m s h o w s c i r c u i t c o n f i g u r a t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g s t o p m o d e , a n d x t a l i s d r i v e n a t " h " l e v e l . e x t a l x t a l o s c i l l a t i o n s t o p c o n t r o l i p i p c m o s s c h m i t t i n p u t m a s k o p t i o n o p * p u l l - u p t r a n s i s t o r a p p r o x i m a t e l y 3 0 0 k w ( v d d = 4 . 5 t o 5 . 5 v ) a p p r o x i m a t e l y 5 0 0 k w ( v d d = 3 . 0 t o 3 . 6 v ) * pin circuit format after a reset
? 14 CXP922032 absolute maximum ratings item supply voltage input voltage output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ref av ss v in v out i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 av ss to +7.0 * 1 av ss to +7.0 ?.3 to +0.3 ?.3 to +7.0 * 2 ?.3 to +7.0 * 2 ? ?0 15 20 130 ?0 to +75 ?5 to +150 600 v v v v v v ma ma ma ma ma c c mw output (value per pin) total for all output pins all pins excluding large current output pins (value per pin) large current output pins * 3 (value per pin) total for all output pins qfp-100p-l01 symbol rating unit remarks * 1 av dd must be the same voltage. * 2 v in and v out must not exceed v dd + 0.3v. * 3 the large current drive transistor is n-ch transistor of pd and pe. note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. (v ss = 0v reference)
? 15 CXP922032 item supply voltage v dd av dd v ih v ihs v ihex v il v ils v ilex topr high level input voltage low level input voltage operating temperature symbol min. 3.0 2.7 2.7 2.5 2.7 2.7 0.7v dd 0.8v dd 0.8v dd 0.7v dd 0 0 0 ?.3 ?.3 ?0 5.5 5.5 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.2v dd 0.3v dd 0.2v dd +75 v v v v v v v v v v v v v v v c guaranteed operation range for 1/16 frequency dividing clock or sleep mode guaranteed data hold range during stop mode * 1 * 2 , * 4 * 2 , * 5 cmos schmitt input * 3 extal * 2 , * 4 * 2 , * 5 cmos schmitt input * 3 extal * 4 extal * 5 max. unit remarks * 1 av dd and v dd must be the same voltage. * 2 pa, pb, pc, pd, pe, pg, ph2, ph6, pi0, pi2, pi3, pj for normal input port. * 3 pf0 to pf5, ph0, ph1, ph3 to ph5, ph7, pi1, pi4 to pi7, cs0, si0, sck0, rst. * 4 when the supply voltage (v dd ) is within the range of 4.5 to 5.5v. * 5 when the supply voltage (v dd ) is within the range of 2.7 to 5.5v. (v ss = 0v reference) guaranteed operation range for 2, 4 and 8 frequency dividing clocks recommended operating conditions f ex = 20mhz or less f ex = 12mhz or less av ref
? 16 CXP922032 electrical characteristics dc characteristics (v dd = 4.5 to 5.5v) (topr = ?0 to +75 c, v ss = 0v reference) high level output voltage v oh v ol i ihe i ile i ilr i il low level output voltage pa to pe, pf6, pf7, pg to pj, so0, sck0 rst * 1 pa to pe * 2 , pg to pj * 2 pa to pe * 2 , pf0 to pf5, pf7, pg to pj * 2 , an0 to an3, cs0, si0, so0, sck0, rst * 1 item symbol pins conditions min. clock 1mhz 0v for all pins excluding measured pins supply current * 3 i dd * 4 i iz i dds1 i dds2 c in input current typ. max. unit * 1 rst specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. * 2 pa to pe and pg to pj specify the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. * 3 when all output pins are open. * 4 when the upper two bits (pck1, pck0) of the clock control register (clc: 0002feh) are set to "00" and the lsi is operated in high-speed mode (2 frequency dividing clock). v dd = 5 0.5v, 20mhz crystal oscillation (c 1 = c 2 = 10pf) v dd = 5 0.5v, 20mhz crystal oscillation (c 1 = c 2 = 10pf), sleep mode v dd , v ss input capacitance v dd = 5.5v, v il = 0.4v v dd = 5.5v, v il = 0.4v v dd = 4.5v, v ih = 4.0v v dd = 5.5v, v i = 0, 5.5v i/o leakage current 40 8 10 1.5 40 ?0 ?00 ?5 10 65 14 10 20 v a a a a a a ma ma a pf v dd = 5.5v, stop mode pa to pe, pf0 to pf5, pg to pj, an0 to an3, cs0, si0, sck0, extal, rst v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma 4.0 3.5 0.5 ?.5 ?.5 ?.78 v v v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v 0.4 0.6 v v pa to pe, pf6, pf7, pg to pj, so0, sck0 pd, pe extal
? 17 CXP922032 dc characteristics (v dd = 3.0 to 3.6v) (topr = ?0 to +75 c, v ss = 0v reference) high level output voltage v oh v ol i ihe i ile i ilr i il low level output voltage pa to pe, pf6, pf7, pg to pj, so0, sck0 rst * 1 pa to pe * 2 , pg to pj * 2 pa to pe * 2 , pf0 to pf5, pf7, pg to pj * 2 , an0 to an3, cs0, si0, so0, sck0, rst * 1 item symbol pins conditions min. clock 1mhz 0v for all pins excluding measured pins v dd , v ss i dd * 4 i iz i dds1 i dds2 c in input current typ. max. unit * 1 rst specifies the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. * 2 pa to pe and pg to pj specify the input current when pull-up resistor has been selected; the leakage current when no resistor has been selected. * 3 when all output pins are open. * 4 when the upper two bits (pck1, pck0) of the clock control register (clc: 0002feh) are set to "00" and the lsi is operated in high-speed mode (2 frequency dividing clock). v dd = 3.3 0.3v, 20mhz crystal oscillation (c 1 = c 2 = 10pf) v dd = 3.3 0.3v, 20mhz crystal oscillation (c 1 = c 2 = 10pf), sleep mode supply current * 3 input capacitance v dd = 3.6v, v il = 0.3v v dd = 3.6v, v il = 0.3v v dd = 3.0v, v ih = 2.7v v dd = 3.6v, v i = 0, 3.6v i/o leakage current 0.3 ?.3 ?.7 ?.0 22 4.5 10 1.0 20 ?0 ?00 ?0 10 40 8 10 20 v a a a a a a ma ma a pf v dd = 3.6v, stop mode pa to pe, pf0 to pf5, pg to pj, an0 to an3, cs0, si0, sck0, extal, rst v dd = 3.0v, i oh = ?.15ma v dd = 3.0v, i oh = ?.5ma 2.7 2.3 v v v dd = 3.0v, i ol = 1.2ma v dd = 3.0v, i ol = 1.6ma v dd = 3.0v, i ol = 5.0ma v dd = 3.6v, v ih = 3.6v v dd = 3.6v, v il = 0.3v 0.3 0.5 v v pa to pe, pf6, pf7, pg to pj, so0, sck0 pd, pe extal
? 18 CXP922032 ac characteristics (1) clock timing (topr = ?0 to +75 c, v dd = 2.7 to 5.5v, v ss = 0v reference) item main clock base oscillation frequency main clock base oscillation input pulse width main clock base oscillation input rise time, fall time f ex t xl , t xh t xr , t xf xtal extal extal extal fig.1, fig.2 fig.1, fig.2 external clock drive fig.1, fig.2 external clock drive 1 1 23 37.5 20 12 100 mhz ns ns symbol pins conditions min. max. typ. unit note) t sys indicates the four values below according to the upper two bits (pck1,pck0) of the clock control register (clc: 0002feh). t sys [ns] = 2/f ex (pck1, pck0 = 00), 4/f ex (pck1, pck0 = 01), 8/f ex (pck1, pck0 = 10), 16/f ex (pck1, pck0 = 11) e x t a l 1 / f e x t x h t x f t x l t x r 0 . 7 v d d 0 . 3 v d d ( v d d = 4 . 5 t o 5 . 5 v ) 0 . 2 v d d ( v d d = 2 . 7 t o 5 . 5 v ) fig.2. oscillator connection and clock applied conditions o s c i l l a t o r c o n n e c t i o n e x a m p l e o f m a i n o s c i l l a t i o n c i r c u i t e x t a l x t a l c 1 c 2 e x t a l x t a l c o n n e c t i o n e x a m p l e o f e x t e r n a l c l o c k 7 4 h c 0 4 fig.1. clock timing v dd = 3.0 to 5.5v v dd = 3.0 to 5.5v
? 19 CXP922032 fig.3. event count input timing e c 0 t e h t e l 0 . 8 v d d 0 . 2 v d d e c 1 (2) event count input (topr = ?0 to +75 c, v dd = 2.7 to 5.5v, v ss = 0v reference) item event count input clock pulse width t eh , t el ec0, ec1 fig.3 t sys + 100 ns symbol pins conditions min. max. unit fig.4. interruption input timing 0 . 2 v d d t i h t i l 0 . 8 v d d n m i i n t 0 t o i n t 7 k s 0 t o k s 6 fig.5. reset input timing 0 . 2 v d d r s t t r s t (3) interruption and reset input (topr = ?0 to +75 c, v dd = 2.7 to 5.5v, v ss = 0v reference) item external interruption high, low level width t ih , t il t rst nmi int0 to int4 ks0 to ks6 int0, int1, int4 rst main mode sleep mode stop mode noise filter selected fig.5 f ps4 ps6 ns s ns ns t sys + 100 1 2 t sys + 100 32/f ex + 100 128/f ex + 100 3 t sys + 200 reset input low level width symbol pins conditions min. max. unit
? 20 CXP922032 conversion time sampling time reference input voltage analog input voltage av ref current t conv t samp v ref v ian i ref i refs av ref v dd = av dd = av ref = 5.0v linearity error absolute error resolution 1.0 10 31/f adc * 10/f adc * av dd ?0.5 0 main mode sleep mode stop mode item symbol pins conditions min. typ. max. unit bits (4) a/d converter characteristics (topr = ?0 to +75 c, v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , v ss = av ss = 0v reference) 8 2 lsb lsb s s v v ma a 3 0.6 av ref an0 to an7 conversion time sampling time reference input voltage analog input voltage av ref current t conv t samp v ref v ian i ref i refs av ref v dd = av dd = av ref = 3.3v linearity error absolute error resolution 0.7 10 31/f adc * 10/f adc * av dd ?0.3 0 main mode sleep mode stop mode item symbol pins conditions min. typ. max. unit bits (topr = ?0 to +75 c, v dd = av dd = 3.0 to 3.6v, av ref = 2.7 to av dd , v ss = av ss = 0v reference) 8 2 lsb lsb s s v v ma a 3 0.4 av ref an0 to an7
? 21 CXP922032 fig.6. definition of a/d converter terms f f h f e h 0 1 h 0 0 h a n a l o g i n p u t l i n e a r i t y e r r o r d i g i t a l c o n v e r s i o n v a l u e f f h ( 1 0 0 h ) f e h 0 1 h 0 0 h a n a l o g i n p u t d i g i t a l c o n v e r s i o n v a l u e a b s o l u t e e r r o r v r e f a b s o l u t e e r r o r v z t * 1 v f t * 2 * 1 v z t : v a l u e a t w h i c h t h e d i g i t a l c o n v e r s i o n v a l u e c h a n g e s f r o m 0 0 h t o 0 1 h a n d v i c e v e r s a . * 2 v f t : v a l u e a t w h i c h t h e d i g i t a l c o n v e r s i o n v a l u e c h a n g e s f r o m f e h t o f f h a n d v i c e v e r s a . * f adc indicates the below values due to the contents of bit 6 (cks) of the a/d control register (adc: 000131h). when ps3 is selected, f adc = f ex /8 when ps4 is selected, f adc = f ex /16 however, when ps3 is selected, f ex is 12mhz or less.
? 22 CXP922032 external start transfer mode (sck = output mode) external start transfer mode (sck = output mode) external start transfer mode external start transfer mode external start transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode note) the load condition for the sck output mode and so output delay time is 50pf+1ttl. (5) serial transfer (ch0, ch1, ch2) (topr = ?0 to +75 c, v dd = 4.5 to 5.5v, v ss = 0v reference) item cs ? sck delay time cs - ? sck float delay time cs ? so delay time cs - ? so float delay time cs high level width sck cycle time sck high, low pulse width si input data setup time (for sck - ) si input data hold time (for sck - ) sck ? so delay time minimum interval time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso t int symbol pins min. 1.5 t sys + 100 1.5 t sys + 100 1.5 t sys + 100 1.5 t sys + 100 t sys + 100 50 t sys + 100 2 t sys + 150 8/f ex t sys + 60 4/f ex ?25 50 100 t sys + 100 50 3 t sys + 100 8/f ex ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns max. unit conditions sck0 sck1 sck2 sck0 sck1 sck2 so0 so1 so2 so0 so1 so2 cs0 cs1 cs2 sck0 sck1 sck2 sck0 sck1 sck2 si0 si1 si2 si0 si1 si2 so0 so1 so2 sck0 sck1 sck2
? 23 CXP922032 external start transfer mode (sck = output mode) external start transfer mode (sck = output mode) external start transfer mode external start transfer mode external start transfer mode input mode output mode input mode output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode sck input mode sck output mode (topr = ?0 to +75 c, v dd = 3.0 to 3.6v, v ss = 0v reference) item cs ? sck delay time cs - ? sck float delay time cs ? so delay time cs - ? so float delay time cs high level width sck cycle time sck high, low pulse width si input data setup time (for sck - ) si input data hold time (for sck - ) sck ? so delay time minimum interval time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso t int symbol pins min. 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 1.5 t sys + 200 t sys + 200 80 t sys + 200 2 t sys + 200 8/f ex t sys + 80 4/f ex ?50 80 150 t sys + 120 70 3 t sys + 150 8/f ex ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns max. unit conditions sck0 sck1 sck2 sck0 sck1 sck2 so0 so1 so2 so0 so1 so2 cs0 cs1 cs2 sck0 sck1 sck2 sck0 sck1 sck2 si0 si1 si2 si0 si1 si2 so0 so1 so2 sck0 sck1 sck2 note) the load condition for the sck output mode and so output delay time is 50pf.
? 24 CXP922032 fig.7. serial transfer ch0, ch1, ch2 timing c s 0 c s 1 c s 2 s c k 0 s c k 1 s c k 2 s i 0 s i 1 s i 2 s o 0 s o 1 s o 2 s c k 0 s c k 1 s c k 2 t i n t 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d t d c s o f 0 . 2 v d d 0 . 8 v d d t s i k t k s i 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d t k h t d c s k f t w h c s t k l t d c s k t k c y t k s o o u t p u t d a t a i n p u t d a t a t d c s o
? 25 CXP922032 (6) remote control reception (topr = ?0 to +75 c, v dd = 2.7 to 5.5v, v ss = 0v reference) item remote control receive high, low level width t rmc rmc main mode sleep mode ps5 selected ps6 selected ps8 selected ns 128/f ex + 100 256/f ex + 100 1024/f ex + 100 symbol pins conditions min. max. unit 0 . 8 v d d r m c 0 . 2 v d d t r m c t r m c fig.8. remote control signal input timing
? 26 CXP922032 e x t a l x t a l c 1 c 2 r d ( i ) m a i n o s c i l l a t i o n c i r c u i t e x t a l x t a l c 1 c 2 r d ( i i ) m a i n o s c i l l a t i o n c i r c u i t fig.9. recommended oscillation circuit appendix * indicates types with on-chip grounding capacitor (c 1 , c 2 ). ccr *** : surface mounted type ceramic oscillator. cl : load capacitor item content reset pin pull-up resistor non-existent existent mask option table manufacturer model f ex (mhz) c 1 (pf) c 2 (pf) rd ( ) circuit example remarks 4 8 10 12 4 8 10 12 16 16 20 20 4 8 10 12 16 20 4 8 10 12 16 20 4 8 10 12 16 20 30 5 27 15 10 10 8 6 22 10 38 ( 20%) 20 ( 20%) 20 ( 20%) 20 ( 20%) 10 ( 20%) 10 ( 20%) 30 5 27 15 10 10 8 6 22 10 38 ( 20%) 20 ( 20%) 20 ( 20%) 20 ( 20%) 10 ( 20%) 10 ( 20%) 0 0 560 330 330 180 0 0 2.2k 0 0 0 0 0 0 0 (i) (ii) (i) (ii) (i) (ii) (i) (i) (ii) v dd = 4.0 to 5.5v cl = 18.5pf cl = 13.0pf cl = 10.5pf cl = 10.5pf cl = 10.0pf cl = 8.5pf cl = 16pf v dd = 3.0 to 5.5v cl = 12pf v dd = 3.5 to 5.5v v dd = 3.5 to 5.5v murata mfg co., ltd. river eletec co., ltd. kinseki ltd. tdk corporation csa4.00mg csa8.00mtz093 csa10.0mtz093 csa12.0mtz093 cst4.00mgw * cst8.00mtw093 * cst10.0mtw093 * cst12.0mtw093 * csa16.00mxz040 cst16.00mxw0c1 * csa20.00mxz040 cst20.00mxw0h1 * hc-49/u03 hc49/u-s ccr4.0mc3 * ccr8.0mc5 * ccr10.0mc5 * ccr12.0mc5 * ccr16.0mc6 * ccr20.0mc6 *
? 27 CXP922032 characteristics curve 5 0 4 0 3 0 2 5 2 0 i d d s u p p l y c u r r e n t [ m a ] 1 5 1 0 8 6 5 3 2 3 4 v d d s u p p l y v o l t a g e [ v ] i d d v s . v d d ( f e x = 2 0 m h z , t o p r = 2 5 c , t y p i c a l ) 5 6 4 2 f r e q u e n c y d i v i d i n g m o d e 4 f r e q u e n c y d i v i d i n g m o d e 8 f r e q u e n c y d i v i d i n g m o d e 1 6 f r e q u e n c y d i v i d i n g m o d e s l e e p m o d e 4 0 3 8 3 6 3 4 3 2 3 0 2 8 2 6 2 4 2 2 i d d s u p p l y c u r r e n t [ m a ] 2 0 1 8 1 6 1 4 1 2 1 0 8 6 4 2 0 5 1 0 f e x m a i n c l o c k b a s e o s c i l l a t i o n f r e q u e n c y [ m h z ] i d d v s . f e x ( v d d = 5 v , t o p r = 2 5 c , t y p i c a l ) 1 5 2 0 0 2 f r e q u e n c y d i v i d i n g m o d e 4 f r e q u e n c y d i v i d i n g m o d e 8 f r e q u e n c y d i v i d i n g m o d e 1 6 f r e q u e n c y d i v i d i n g m o d e s l e e p m o d e
? 28 CXP922032 s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 2 3 . 9 0 . 4 q f p - 1 0 0 p - l 0 1 1 0 0 p i n q f p ( p l a s t i c ) 2 0 . 0 0 . 1 + 0 . 4 0 . 1 5 0 . 0 5 + 0 . 1 1 5 . 8 0 . 4 1 7 . 9 0 . 4 1 4 . 0 0 . 1 + 0 . 4 2 . 7 5 0 . 1 5 + 0 . 3 5 a 0 . 6 5 m 0 . 1 3 q f p 1 0 0 - p - 1 4 2 0 1 . 7 g 1 1 0 0 8 1 8 0 5 1 5 0 3 1 3 0 0 . 3 0 . 1 + 0 . 1 5 d e t a i l a 0 t o 1 0 0 . 8 0 . 2 ( 1 6 . 3 ) 0 . 1 5 0 . 1 0 . 0 5 + 0 . 2 package outline unit: mm

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